The electrostatic discharge (ESD) robustness of CMOS ICs has been found to be seriously degraded by advanced deep-submicron CMOS technologies, as reported, for example, by S. Voldman and V. Gross in "Scaling, optimization and design consideration of electrostatic discharge protection circuits in CMOS technology," 1993 EOS/ESD Symposium Proceedings, pp. 251-260, and A. Amerasekera and C. Duvvury in "The impact of technology scaling on ESD robustness and protection circuit design," 1994 EOS/ESD Symposium Proceedings, pp. 237-245. As a result, it is necessary to improve ESD protection for the output buffers in these ICs through either process modification, such as discussed by S. Daniel and G. Krieger, in "Process and design optimization for advanced CMOS I/O ESD protection devices," 1990 EOS/ESD Symposium Proceedings, pp. 206-213, or by more effective ESD protection circuit design. To improve the ESD robustness of the output transistors in such circuits, the symmetrical layout structure has been greatly emphasized to realize large-dimension output transistors for ensuring the uniform turn-on phenomenon along the multiple fingers of the output transistors, as explained, for instance, by T. L. Polgreen and A. Chattejee, in "Improving the ESD failure threshold of silicided nMOS output transistors by ensuring uniform current flow," IEEE Trans. Electron Devices, vol.39, pp. 379-388, 1992, and S. G. Beebe, in "Methodology for layout design and optimization of ESD protection transistors," 1996 EOS/ESD Symposium Proceedings, pp. 265-275. To additionally enhance the uniform turn-on phenomenon among the multiple fingers of an output NMOS, a dynamic-gate-coupling design to achieve uniform ESD power distribution of the large-dimension output NMOS has been reported by C. Duvvury and C. Diaz, in "Dynamic gate coupling of NMOS for efficient output ESD protection," Proc. of IRPS, 1992, pp. 141-150.
In practical applications, the output buffers in a cell library have different driving current specifications. For example, the output buffers may have driving capabilities of 2 mA, 4 mA, 8 mA, . . . , or 24 mA as in the TSMC cell library. But, the cell layouts of these output buffers with different driving capabilities are drawn in the same layout style and area. To provide different output driving currents, different fingers of the poly gates in the output buffers, e.g., N-channel-type metal-oxide-semiconductor (NMOS) buffers, are connected to the pre-buffer circuit, while the other unused poly-gate fingers are connected to ground. An example of a typical layout of a finger-type output NMOS with a small driving current is shown in FIG. 1(a), and the equivalent circuit is shown in FIG. 1(b). In FIG. 1(a) there are ten poly-gate fingers (F) in the NMOS layout, but only one poly-gate finger (Mn1) is connected to the pre-buffer circuit (12) to provide the sinking current from the output pad (10). The other nine poly-gate fingers F are unused, but inside the layout, and are all connected to ground. The common grounding of these NMOS fingers, shown as Mn2 in FIG. 1(b), turns them OFF. Due to the asymmetrical connection of these poly-gate fingers F of the output NMOS in the layout, the ESD turn-on phenomena among the fingers are quite different. The Mn1 with a small channel width is often turned ON first and damaged by the ESD voltage, whereas the unused Mn2 with a much larger (9X) channel width is always OFF during the ESD stress. This generally causes a very low ESD level for the output buffer even with a total large device dimension (Mn1+Mn2).
To improve the turn-on uniformity of the output buffers with different driving/sinking currents and also to protect the thinner gate oxide of the output buffers in the TSMC CMOS cell library, it has been suggested that the poly gates of the unused NMOS and/or PMOS in the output buffers be respectively connected to a voltage source VSS and a voltage source VDD, through a small-dimension NMOS Mdn1 and PMOS Mdp1, as shown in FIG. 2 (also see "Electrostatic discharge protection circuit," U.S. Pat. No. 5,086,365 to C. -D. Lien). The small dimension Mdnl (or Mdp1) provides the function of a resistor to protect the thinner gate oxide of unused Mn2 (or Mp2) and also sustains the ESD-transient coupling voltage on the gate of Mn2 (or Mp2) to help the uniform turn-on phenomenon among the multiple fingers of the Mn1 and Mn2 (or Mp1 and Mp2). The small dimension Mdn1 (or Mdp1) cooperating with the parasitic drain-to-gate capacitance Cn2 in Mn2 (or Cp2 in Mp2) performs a gate-coupling effect to turn ON the unused Mn2 (or Mp2) during the ESD stress (see M. -D. Ker et al, "Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC," IEEE Transactions on VLSI Systems, Vol.4, pp. 307-321, 1996).
The ESD test to verify the ESD level of an output pin is shown in FIG. 3, where there are four modes of testing combinations from the output pin to the VDD or VSS pins, i.e., (1) PS-mode, (2) NS-mode, (3) PD-mode, and (4) ND-mode (see EOS/ESD Standard for ESD Sensitivity Testing, EOS/ESD Association, Inc., New York, 1993). In the (4) ND-mode (or the (1) PS-mode) ESD stress, the output PMOS (or NMOS) is reverse biased and broken down by the ESD voltage. But, in the (2) NS-mode (or the (3) PD-mode) ESD stress, the parasitic drain-to-bulk diode in the NMOS (or PMOS) is forward biased to bypass the ESD current. Thus, the worst cases of ESD stresses on an output buffer are the (4) ND- and (1) PS-mode ESD events.
By way of an operating example using the NMOS devices, it will be seen that when a positive ESD voltage attaches to the output pad 10 of FIG. 2, some transient voltage is coupled through the parasitic drain-to-gate capacitors, Cn1 and Cn2, to the gates of Mn1 and Mn2. The gate of Mdn1 is biased at a high voltage because the positive ESD voltage on the pad 10 is also diverted into the VDD power line through the parasitic diode Dp2 in Mp2 (or Dp1 in Mp1). The coupled voltage, through Cn1, on the gate of Mn1 is held on its gate, but the coupled voltage, through Cn2, on the gate of Mn2 is discharged by Mdn1. This causes Mn1 to be triggered ON and damaged by the ESD energy before Mn2 is turned ON. Because Mn1 is designed with a small device dimension for a low driving-current specification (for example, 30/0.5 in the 2-mA output buffer), such an output buffer often has a low ESD level.
The human-body-model (HBM) ESD testing results of the output buffers with different driving currents in the TSMC 0.35-.mu.m CMOS process are summarized in the following Table I.
TABLE I ______________________________________ Output Buffers HBM 2-mA 4-mA 8-mA 12-mA 24-mA ESD Stress Buffer Buffer Buffer Buffer Buffer ______________________________________ ND-Mode 1.5K V 2K V 2.5K V &gt;2.5K V &gt;2.5K V PS-Mode 1.0K V 1.5K V 2.0K V &gt;2.5K V &gt;2.5K V ______________________________________
Table 1 shows the HBM ESD-Sustained Level of the Driving-Current-Prograrnmable Output Buffers with the traditional gate-coupling effect. Due to the different connections on the gates of the output Mn1 and the unused Mn2, the ND-mode (or PS-mode) ESD level of the 2-mA output buffer is only 1.5 KV (or 1.0 KV). While the driving current of the output buffer may be increased by making the device dimension of Mn1 larger, the output buffer will also have a higher ESD level. Although the cell layout areas of the various output buffers (2 mA, 4 mA, . . . , 24 mA) are all the same in the cell library, the ESD levels of these output buffers are quite different. Even when using the small-dimension NMOS Mdn1 (or PMOS Mdp1) to perform the gate-coupling effect to help produce the uniform turn-on between the fingers of Mn1 and Mn2 (or Mp1 and Mp2), the HBM ESD level of the output buffer with a small Mn1 (or Mp1) but a large Mn2 (or Mp2) is still below the general industrial ESD specification of 2.0 KV.
It is therefore an object of the present invention to improve the ESD robustness of driving-current-programmable CMOS output buffers in cell libraries, such as the TSMC cell library.
It is another object of the present invention to effectively improve the ESD level of the CMOS output buffers in cell libraries.
It is a further object of the invention to provide a dynamic-floating-gate arrangement that improves the ESD robustness of driving-current-programmable CMOS output buffers in cell libraries and effectively improves the ESD level of the output buffers.